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(R)
TDA7427
AM-FM RADIO FREQUENCY SYNTHESIZER AND IF COUNTER
ON-CHIP REFERENCE OSCILLATOR AND PROGRAMMABLE IF COUNTER VHF INPUT AND PRECOUNTER FOR FREQUENCIES UP TO 290MHz (SUITABLE FOR DAB APPLICATION) HF INPUT FOR FREQUENCIES UP TO 64MHz (SHORT WAVE BAND) IN-LOCK DETECTOR FOR SEARCH/STOP STATION FUNCTION STAND-BY MODE FOR LOW POWER CONSUMPTION HIGH CURRENT SOURCE FOR 0.5ms LOCK-IN TIME DIGITAL PORT EXTENSION WITH TWO OUTPUTS FOR FLEXIBILITY IN APPLICATION FULLY PROGRAMMABLE BY I2C BUS DESCRIPTION The TDA7427 is a PLL frequency synthesizer BLOCK DIAGRAM
DIP20
SO20
ORDERING NUMBERS: TDA7427(DIP20) TDA7427D (SO20)
with an additional IF counting system that performs all the functions needed in a complete PLL radio tuning system for conventional and high speed RDS tuners. The device has dedicated outputs for IN-LOCK detection and Search/Stop station.
13 FM_IN 16 SWITCH AM/FM HFREF 14 SWITCH SWM/DIR SWITCH SWM/DIR PHASE COMP CHARGE PUMP + VDD1 20 PRECOUNTER :32/33 5 BIT PROG. CNT INLOCK DETECTOR 2 3 SWITCH LP1/LP2 1
DOUT1/INLOCK LP_HC LP_AM LP_FM
AM_IN
17
LPOUT
11 BIT PROG CNT OSCIN OSCOUT 5 6 REF OSCILLATOR 16 BIT PROG CNT
4
VREF
SCL SDA
8 9
I2C BUS INTERFACE
18
GNDan/GNDdig
VDD2 VDD1
19 15 14 BIT PROG CNT TIMER CONTROL TEST LOGIC POWER ON RESET
IF_AM
10 11-21 BIT PROG CNT PORT EXTENSION
IF_FM
11
12
D95AU418B
7 DOUT3
SSTOP
November 1999
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TDA7427
ABSOLUTE MAXIMUM RATINGS
Symbol VDD1 VDD2 Ptot Tstg Tamb Supply Voltage Supply Voltage Total Power Dissipation Storage Temperature Ambient Temperature Parameter Value - 0.3 to + 7 - 0.3 to + 11 300 - 55 to + 150 -40 to + 85 Unit V V mW
o o
C C
PIN CONNECTION
LP_FM LP_HC LP_AM VREF OSCIN OSCOUT DOUT3 SCL SDA IF_AM
1 2 3 4 5 6 7 8 9 10
D95AU373B
20 19 18 17 16 15 14 13 12 11
LPOUT VDD2 GND AM_IN FM_IN VDD1 HFREF DOUT1/INLOCK SSTOP IF_FM
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction-Ambient max DIP20 100 SO20 150 Unit
o
C/W
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TDA7427
PIN DESCRIPTION (TDA7427/D)
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13* 13* 14 15 16 17 18 19 20 SYMBOL DESCRIPTION INPUT/OUTPUT
LP_FM
Filter OPAMP input, charge pump output (FM mode) Filter OPAMP input, charge pump output (high current LP_HC mode) LP_AM Filter OPAMP input, charge pump output (AM mode) VREF OPAMP reference voltage OSCIN Oscillator reference clock input OSCOUT Oscillator output DOUT3 Open collector output SCL I2C bus clock input SDA I2C bus data I/O IF_AM IF counter input (AM mode) IF_FM IF counter input (FM mode) SSTOP IF counter result output DOUT1 Digital output INLOCK Inlock detector output HFREF HF reference VDD1 Positive power supply 5V FM_IN High frequency input FM AM_IN High frequency input AM GND Analog digital ground VDD2 Positive power supply 10V LPOUT Filter input, change pump output
Input Input/output Analog input Analog input Output Push-pull output Output Supply Analog input Analog input Supply Supply
* Pin function is userdefined by software
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TDA7427
ELECTRICAL CHARACTERISTICS (Tamb = 25C; VDD1 = 5V; VDD2 = 10V; fOSC = 4MHz; unless otherwise specified).
Symbol VDD1 VDD2 IDD1 IDD2 IDD1 STB Parameter Supply Voltage Supply Voltage Supply Current Supply Current Supply Current no output load PLL locked Standby mode 2 1 Test Condition Min. 4.5 Typ. 5.0 9.0 4 2 Max. 5.5 11.0 6 3 1 Unit V V mA mA A MHz MHz mVrms mVrms 30 600 3 3 4 4 5 5 mVrms mVrms K K
RF INPUT (AM_IN, FM_IN) fiAM fiFM ViMIN ViMAX ViMIN ViMAX Zin Zin Input Frequency AM Input Frequency FM Min Input Voltage AM Max Input Voltage AM Min Input Voltage FM Max Input Voltage FM Input Impedance FM input Input Impedance AM input Vi = 100mVrms sinusoidal Vi = 100mVrms sinusoidal 0.5 to 16MHz range sinusoidal 0.6 to 16MHz range sinusoidal 70 to 120MHz range sinusoidal 70 to 120MHz range sinusoidal 600 0.5 30 64 200 30
IF COUNTER (IF_AM, IF_FM) fiAM fiAM ViMIN ViMIN ViMAX ViMAX Zin Zin Input Frequency range AM Input Frequency range FM Min Input Voltage AM IF pin Min Input Voltage FM IF pin Max Input Voltage AM IF pin Max Input Voltage FM IF pin Input Inpedance FM IF pin Input Inpedance AM IF pin Vi = 100mVrms Vi = 100mVrms fin = 455kHz fin = 10.7MHz fin = 455kHz fin = 10.7MHz 600 600 3 3 4 4 5 5 0.400 10 11 11 30 30 MHz MHz mVrms mVrms mVrms mVrms K K
BUS INTERFACE Tj fSCL tAA tbuf tHD-START tLOW tHIGH tSU-SDA tHD-DATA tSU-DATA tR tF tSU-STOP tDH Noise Suppression Time Constant on SCL, SDA Input SCL Clock Frequency SCL Low to SDA Data Valid Time the bus must be free for the new transmission START Condition hold time Clock Low Period Clock High Period Start Condition Setup Time Data Input Hold Time Data Input Setup Time SDA & SCL Rise Time SDA & SCL Full Time Stop Condition Setup Time DATA OUT Time 4.7 300 0.3 250 1 300 4.7 4.0 4.7 4.0 4.7 1 50 400 ns kHz ns s s s s s s ns s s s ns
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TDA7427
ELECTRICAL CHARACTERISTICS (continued)
Symbol VIL VIH IIN VOUT Parameter Input Low Voltage Input High Voltage Input Current Output Voltage SDA acknowledge IO = 1.6mA 3 -5 0.15 +5 0.4 Test Condition Min. Typ. Max. 1 Unit V V A V
OSCILLATOR tbu Cin COUT Zin Vin fin Build Up Time Internal Capacitance Internal Capacitance Input Impedance Input Voltage (for Slave Mode) Max Input frequency (for Slave Mode) fosc = 4MHz fosc = 4MHz fIN = 4 to 13MHz (Sinus) capacitance coupling VIN = 600mVPP (Sinus) 300 30 fout = 4MHz 20 20 100 VDD 100 ms pF pF K mVpp MHz
LOOP FILTER (LP_FM, LP_AM, LP_HC, LP_OUT) IIN IIN VOL VOH IOUT IOUT Input Leakage Current (*) Input Leakage Current (*) Output Voltage Low Output Voltage High Output Current Sink Output Current Source VOUT = 0.5 to 9.5V IOUT = -0.1mA IOUT = 0.1mA VOUT = 10V IOUT = -1mA VOUT = 0.5 to 9.5V VDD1*0.2 -1 VIN = GND; PDout = Tristate (1) VIN = VDD1; PDout = Tristate (1) IOUT = -0.2mA IOUT = 0.2mA 9.5 10 10 -1 -1 0.1 0.1 0 10 30 30 1 1 0.5 A A V V mA mA
DOUT1/SSTOP (push-pull outputs) VOL VOH Output Voltage Low Output Voltage High 0.1 4.9 0.2 V V
DOUT3 (open collector output) IOUT VOL IOUT Output leakage Current Output Voltage Low Output Current Sink 0.1 0.2 3 1 0.5 5 mA V mA
1) PD = Phase Detector (*) LP_FM and LP_HC pins only
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GENERAL DESCRIPTION This circuit contains a frequency synthesiser and a loop filter for use in FM/AM radio tuning systems. Only a VCO is required to build a complete PLL system. For auto search/stop operation an IF counter system is available. For FM and SW AM application, the counter works in a two-stage configuration. The first stage is a swallow counter with a two modulus (:32/33) precounter. The second stage is an 11-bit programmable counter. For LW and MW application, a 16-bit programmable counter is available. The circuit receives the scaling factors for the programmable counters and the values of the refer2 ence frequencies via a I C bus interface. The reference frequency is generated by an internal XTAL oscillator followed by the reference divider. The device can operate with XTAL oscillator between 4 and 13MHz either in master mode and in slave mode. The reference and step frequencies are free selectable. (XTAL frequency divided by an integer value). The outputs signals of the phase detector are switching the programmable current sources. The loop filter integrates their currents to a DC voltage. Values of the current sources are programmable by 6 bits also received via the I2C bus. To minimize the noise induced by the digital part of the system, a separate power supply supplies the internal loop filter amplifier. The loop gain can be set for different conditions by setting the current values of the charge/pump generator. IF COUNTER SYSTEM Two separate inputs are available for AM and FM IF signals. The level of integration is adjustable by six different measuring cycle times. The tolerance of the accepted count value is adjustable, to reach an optimum compromise for search speed and precision of the evaluation. For the FM range the center frequency of the measured count value is adjustable in 32 steps, to get the possibility of fitting the IF filter tolerance. In the AM range an IF frequency of 448 to 479KHz ( 10.684 to 10.715MHz for AM up-conversion) with 1KHz steps is available. PLL FREQUENCY SYNTHESIZER Input Amplifiers The signals applied on AM and FM inputs are amplified to get a logic level in order to drive the frequency dividers. The typical input impedance for FM and AM inputs is 4k.
Table 1. Address Organization
MSB FUNCTION PLL CHARGE PUMP PLL COUNTER PLL COUNTER PLL REF COUNTER PLL REF COUNTER PLL LOCK DETECT IFC REF COUNTER IFC REF COUNTER IFC CONTROL IFC CONTROL OSC ADJUST PORT EXTENSION SUBAD 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH BIT 7 LPIN1/2 PC7 PC15 RC7 RC15 LDENA IRC7 IFCM1 IFENA IFS2 BIT 6 CURRH PC6 PC14 RC6 RC14 INLOCK IRC6 IFCM0 IFS1 BIT 5 B1 PC5 PC13 RC5 RC13 D3 IRC5 IRC13 IFS0 BIT 4 B0 PC4 PC12 RC4 RC12 D2 IRC4 IRC12 CF4 OSC4 BIT 3 A3 PC3 PC11 RC3 RC11 D1 IRC3 IRC11 CF3 OSC3 BIT 2 A2 PC2 PC10 RC2 RC10 D0 IRC2 IRC10 EW2 CF2 OSC2 DOUT3 BIT 1 A1 PC1 PC9 RC1 RC9 PM1 IRC1 IRC9 EW1 CF1 OSC1 LSB BIT 0 A0 PC0 PC8 RC0 RC8 PM0 IRC0 IRC8 EW0 CF0 OSC0 DOUT1
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Figure 1. FM and AM (SW) operation (swallow mode)
REGISTER R0 ...R15 PREDIVIDER :R
OSC IN
fref fsyn
PD
TO CHARGE PUMP
REGISTER PC0 ...PC4 COUNTER A
AM IN
REGISTER PC5 ... P15 COUNTER :B
PRESCALER M/M+1 FM IN
D95AU375A
Table 2. Control Register Functions.
REGISTER NAME PC RC IRC IFCM EW IFENA CF IFS PM D LPIN1/2 PLLSTOP A B LDENA CURRH OSC DOUT1 DOUT3 INLOCK Reference counter PLL Reference counter IF IF counter mode selector Frequency error window IF counter Enable IFRC Center frequency IF counter Sampling time IF counter Stby, FM, AM, AM swallow mode selector Programmable delay and phase error for lock detector Loop filter input select PLL stop Charge pump high current Charge pump low current Lock detector enable Set current high Oscillator adjust Push pull output 5V Open collector output Lock detector output FUNCTION Programmable counter for VCO frequency
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TDA7427
Figure 2. AM direct mode operation for SW, MW and LW
OSC IN
PREDIVIDER :R REGISTER RC0 ... RC15
fref fsyn
PHASE DETECTOR
TO CHARGE PUMP
AM IN
REGISTER PC0 ... PC15 PRESCALER :C
FM IN
D95AU376A
DIVIDER FROM VCO FREQUENCY TO REFERENCE FREQUENCY This divider provides a low frequency fSYN which phase is compared with the reference frequency fREF . It is controlled by the registers PC0 to PC4 and PC5 to PC15 OPERATING MODES Four operating modes are available fo PLL; they are user programmable with the Mode PM registers (see table):
PM0 0 1 0 1 PM1 0 0 1 1 Operating Mode Standby AM (swallow) AM (direct) FM
Dividing range calculation : fVCO = [ 33 A + (B + 1 - A) 32 ] fREF fVCO = (32 B + A + 32) fREF Important:for correct operationA 32, B A,with A andB variable values of the dividers). - AM direct mode: the AM signal is applied directly to the 16 bit static divider 'C'. (PC0 to PC15) fOSC = (R + 1) f REF Dividing range: fVCO = (C + 1) fREF THREE STATE PHASE COMPARATOR The phase comparator generates a phase error signal according to phase difference between fSYN and fREF. This phase error signal drives the charge pump current generator (fig. 3) CHARGE PUMP CURRENT GENERATOR This stage generates signed pulses of current. The phase error signal decides the duration and polarity of those pulses. The current absolute values are programmable by A0, A1, A2 registers for high current and B0, B1, registers for low current. LOW NOISE CMOS OP-AMP An internal voltage divider at pin VREF connects the positive input of the low noise Op-Amp. The charge pump output connects the negative input. This internal amplifier in cooperation with external components can provide an active filter.
- Standby mode: in this mode all device functions are stopped. This allows low current consumption without loss of information in all registers. The pin LP-OUT is forced to 0V, and all data registers are set to EFH. The oscillator keeps running. - FM and AM (SW) Swallow Mode (SW): in this mode the FM or AM signal is applied to a 32/33 prescaler, which is controlled by a 5 bit divider 'A'.The 5 bit register (PC0 to PC4) controls this divider. In parallel the output of the prescaler is connected to a 11 bit divider 'B'. (PC5 to PC15). fOSC = (R+1) fREF
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TDA7427
Figure 3. Phase comparator waveforms
Figure 4. IF Counter internal block diagram
IFENA EW-REGISTER
IF-AM
11-21 BIT COUNTER
ZD
IF-FM
CF-REGISTER
UP/DOWN COUNTER
OSC
14 BIT COUNTER
3 BIT COUNTER
DECODE
SSTOP
IFC-REGISTER
IFS-REGISTER
D95AU377A
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The negative input is switchable to three input pins ( LPIN 1, LPIN 2 and LPIN 3) to increase the flexibility in application. This feature allows two separate active filters for different applications A logical "1" in the LPIN 1/2 register activates pin LPIN 1, otherwise pin LPIN 2 is active. While the high current mode is activated LPIN 3 is switched on. INLOCK DETECTOR The charge pump can be switched in low current mode either via software or automatically by the inlock detector by setting bit LDENA to "1". The charge pump is forced in low current mode when a phase difference of 10-40 nsec is reached. A phase difference larger then the programmed values will switch the charge pump immediately in the high current mode. Programmable delays are available for inlock detection. IF COUNTER SYSTEM (AM/FM/AM - UPC MODES) The if counter works in modes controlled by IFCM register (see table):
IFCM1 0 0 1 1 IFCM0 0 1 0 1 FUNCTION NOT USED FM MODE AM MODE 10.7MHz AM UP CONVERSION MODE
mode a 1KHz signal is generated. This is followed by an asynchronous divider to generate different sampling times (see fig. 4). Intermediate Frequency Main Counter This counter is a 11/21 bits synchronous autoreload down-counter. Four bits are programmable to have the possibility for an adjust to the frequency of the CF filter. The counter length is automatically adjusted to the chosen sampling time and the counter mode (AM, FM, AM-UPC). At the start the counter will be loaded with a defined value which is an equivalent to the divider value (tsample fIF). If a correct frequency is applied to the IF counter frequency inputs IF-AM IF-FM, at the end of the sampling time the main counter is changing its state from 0 H to 1FFFFFH. This is detected by a control logic. The frequency range inside which a successful count results is detected is adjustable by bits EW 0,1,2. Adjustment of the Measurement Sequence Time The precision of the measurements is adjustable by controlling the discrimination window . This is adjustable by programming the control registers EW0...EW2. The measurement time per cycle is adjustable by setting the Register IFS0 - IFS2. Adjust of the Frequency Value The center frequency of the discrimination window is adjustable by the control register "CF0" to "CF4". (see data byte specification). Port Extension and additional functions One digital open collector output and one digital push-pull output are available in application mode. This digital ports are controlled by the data bits DOUT1 and DOUT3.
Typical input impedance for IF inputs is 4K. A sample timer to generate the gate signal for the main counter is build with a 14-bit programmable counter to have the possibility to use any crystal oscillator frequency. In FM mode 6.25KHz in AM Figure 5. I2C Bus timing diagram
tHIGH tR
tLOW
tR
SCL
tSU-STA tHD-DAT tHD-STA tSD-DAT tSUBTOP
SDA IN
tAA tDH ttxt
SDA OUT
D95AU378
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TDA7427
I2C BUS INTERFACE DESCRIPTION The TDA7427 supports the I2C bus protocol. This protocol defines any device that sends data into the bus as a transmitter and the receiving device as the receiver. The device that controls the transfer is the master and the device being controlled is the slave. The master always initiates data transfer and provides the clock to transmit or receive operations. Data Transition Data transition on the SDA line must only occur when the clock SCL is low. SDA transitions while SCL is high will be interpreted as START or STOP condition. Start Condition A start condition is defined by a HIGH to LOW transition of the SDA line while SCL is at a stable HIGH level. This START condition must precede any command and initiate a data transfer onto the bus. The TDA7427 continuously monitors the SDA and SCL lines for a valid START and will not response to any command if this condition has not been met. Stop Condition A STOP condition is defined by a LOW to HIGH transition of the SDA while the SCL line is at a stable HIGH level. This condition terminate the communication between the devices and forces the bus interface of the TDA7427into the initial condition. Acknowledge Indicates a successful data transfer. The transmitFigure 6. Application with two loop filters
FM VCO +10V 10F VDD1 VDD2 SCL CONTROLLER SDA 19 8 9 10 100nF AM-FM IF 1nF 10nF IF_AM 11 10nF IF_FM 16 FM_IN 17 AM_IN 20 10nF 3.9K 100nF 820 Utun LPOUT 1nF 3.3nF AM VCO
ter will release the bus after sending 8 bit of data. During the 9th clock cycle the receiver will pull the SDA line to LOW level to indicate it has receive the eight bits of data correctly. Data transfer During data transfer the TDA7427 samples the SDA line on the leading edge of the SCL clock. Therefore, for proper device operation the SDA line must be stable during the SCL LOW to HIGH transition. Device Addressing To start the communication between two devices, the bus master must initiate a start instruction sequence, followed by an eight bit word corresponding to the address of the device it is addressing. The most significant 6 bits of the slave address are the device type identifier. The TDA7427 frequency synthesizer device type is fixed as "110001" The next significant bit is used to address a particular device of the previous defined type connected to the bus. The state of the hardwired A0 pin defines the state of this address bit. So up to two devices could be connected on the same bus. The last bit of the instruction defines the type of operation to be performed: - When set to "1", a read operation is selected - When set to "0", a write operation is selected The chip selection is accomplished by setting the bit of the chip address to the corresponding status of the A0 input. All TDA7427 connected to the bus will compare their own hardwired address with the slave ad-
1 LP_FM 27K 15K 100K 68nF
TDA7427
+5V 100nF VDD1 10F VREF 100nF 5 OSCIN 4MHz
D95AU379B
2
6.8nF
FM:50KHz
LP_HC LP_AM
15
3
4 13 6 OSCOUT 10nF 14 HFREF 7 12 DOUT3 SSTOP
6.8nF INLOCK/DOUT1
AM:1KHz
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TDA7427
dress being transmitted. After this comparison, the TDA7427 will generate an "acknowledge" on the SDA line and will perform either a read or write operation according to the state of R/W bit. Write Operation Following a START condition the master sends a slave address word with the R/W bit set to "0". The TDA7427 will "acknowledge" after this first transmission and wait for a second word (the word address field). This 8 bit address field provides an access to any of the 8 internal addresses. Upon receipt of the word address the TDA7427 slave device will respond with an "acknowledge". At this time, all the
CHIP ADDRESS MSB S 1 1 0 0 0 1 LSB MSB T T I
following words transmitted to the TDA7427 will be considered as Data. The internal address will be automatically incremented. After each word receipt the TDA7427 will answer with an "acknowledge". SOFTWARE SPECIFICATION 2 I C Protocol The interface protocol comprises: A start condition (s) A chip address byte (the LSB determines read/write transmission) A sub-address byte. A sequence of data (N-bytes + acknowledge) A stop condition (P)
DATA 1 to DATA n LSB A3 A2 A1 A0 ACK MSB DATA LSB
ACK P
SUBADDRESS
0 R/W ACK T
ACK = Acknowledge S = Start P = Stop I = Auto Increment T = used for testing (in application mode they have to be " 0") MAX CLOCK SPEED 400kbits/s
CHIP ADDRESS
MSB 1 1 0 0 0 1 0 LSB 0
SUBADDRESS
MSB T3 T2 T1 I A3 0 0 0 0 0 0 0 0 1 1 1 1 A2 0 0 0 0 1 1 1 1 0 0 0 0 A1 0 0 1 1 0 0 1 1 0 0 1 1 LSB A0 0 1 0 1 0 1 0 1 0 1 0 1 FUNCTION Charge pump control PLL counter 1 (LSB) PLL counter 2 (MSB) PLL reference counter 1 (LSB) PLL reference counter 2 (MSB) PLL lockdetector control and PLL mode select IFC reference counter 1 (LSB) IFC reference counter 2 (MSB) and IFC mode select IF counter control 1 IF counter control 2 Oscillator adjust Port extension page mode off page mode enabled
0 1
T1, T2, T3 used for testing, in application mode they have to be "0"
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TDA7427
Data Byte Specification CHARGE PUMP CONTROL
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 1 0 LPIN1/2 CURRH B1 B0 A3 A2 A1 A0 0 1 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 High current = 0mA High current = 0.5mA High current = 1.0mA High current = 1.5mA High current = 2.0mA High current = 2.5mA High current = 3.0mA High current = 3.5mA High current = 4.0mA High current = 4.5mA High current = 5.0mA High current = 5.5mA High current = 6.0mA High current = 6.5mA High current = 7.0mA High current = 7.5mA Low current = 0A Low current = 50A Low current = 100A Low current = 150A Select low Current Select high Current Select loop filter LP_FM Select loop filter LP_AM Subaddress = 00H FUNCTION
PLL COUNTER 1 (LSB)
MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 D4 0 0 0 D3 0 0 0 D2 0 0 0 D1 0 0 1 LSB D0 0 1 0 LSB = 0 LSB = 1 LSB = 2 FUNCTION
1 1 1 1 PC7
1 1 1 1 PC6
1 1 1 1 PC5
1 1 1 1 PC4
1 1 1 1 PC3
1 1 1 1 PC2
0 0 1 1 PC1
0 1 0 1 PC0
LSB = 252 LSB = 253 LSB = 254 LSB = 255 Bit name Subaddress = 01H
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TDA7427
PLL COUNTER 2 (MSB)
MSB D7 0 0 0 1 1 1 1 PC15 D6 0 0 0 1 1 1 1 PC14 D5 0 0 0 1 1 1 1 PC13 D4 0 0 0 1 1 1 1 PC12 D3 0 0 0 1 1 1 1 PC11 D2 0 0 0 1 1 1 1 PC10 D1 0 0 1 0 0 1 1 PC9 LSB D0 0 1 0 0 1 0 1 PC8 MSB = 0 MSB = 256 MSB = 512 MSB = 64768 MSB = 65024 MSB = 65280 MSB = 65536 Bit name Subddress = 02H FUNCTION
Swallow mode: fvco/fsyn = LSB + MSB + 32 Direct mode: fvco/fsyn = LSB + MSB + 1
PLL REFERENCE COUNTER 1 (LSB)
MSB D7 0 0 0 1 1 1 1 RC7 D6 0 0 0 1 1 1 1 RC6 D5 0 0 0 1 1 1 1 RC5 D4 0 0 0 1 1 1 1 RC4 D3 0 0 0 1 1 1 1 RC3 D2 0 0 0 1 1 1 1 RC2 D1 0 0 1 0 0 1 1 RC1 LSB D0 0 1 0 0 1 0 1 RC0 LSB = 0 LSB = 1 LSB = 2 LSB = 252 LSB = 253 LSB = 254 LSB = 255 Bit name Subaddress =03H FUNCTION
PLL REFERENCE COUNTER 2 (MSB)
MSB D7 0 0 0 1 1 1 1 RC15 D6 0 0 0 1 1 1 1 RC14 D5 0 0 0 1 1 1 1 RC13 D4 0 0 0 1 1 1 1 RC12 D3 0 0 0 1 1 1 1 RC11 D2 0 0 0 1 1 1 1 RC10 D1 0 0 1 0 0 1 1 RC9 LSB D0 0 1 0 0 1 0 1 RC8 MSB = 0 MSB = 256 MSB = 512 MSB = 64768 MSB = 65024 MSB = 65280 MSB = 65536 Bit name Subddress = 04H FUNCTION
fOSC/fREF = LSB + MSB + 1
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TDA7427
LOCK DETECTOR & PLL MODE CONTROL
MSB D7 D6 D5 D4 D3 D2 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 LDENA INLOCK D3 D2 D1 D0 PM1 PM0 0 1 0 1 0 1 0 1 LSB D0 0 1 0 1 PLL standby mode PLL AM swallow mode PLL AM direct mode PLL FM mode PD phase difference threshold 10ns PD phase difference threshold 20ns PD phase difference threshold 30ns PD phase difference threshold 40ns Not used in application mode Activation delay = 4 fref Activation delay = 6 fref Activation delay = 8 fref Digital output 1 at pin "dout1/inlock" Inlock information at pin "dout1/inlock" No lock detector controlled chargepump Lock detector controlled chargepump Bit name Subaddress = 05H FUNCTION
IF COUNTER REFERENCE CONTROL 1 (LSB)
MSB D7 0 0 0 1 1 1 1 IRC7 D6 0 0 0 1 1 1 1 IRC6 D5 0 0 0 1 1 1 1 IRC5 D4 0 0 0 1 1 1 1 IRC4 D3 0 0 0 1 1 1 1 IRC3 D2 0 0 0 1 1 1 1 IRC2 D1 0 0 1 0 0 1 1 IRC1 LSB D0 0 1 0 0 1 0 1 IRC0 LSB = 0 LSB = 1 LSB = 2 LSB = 252 LSB = 253 LSB = 254 LSB = 255 Bit name Subaddress = 06H FUNCTION
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TDA7427
IF COUNTER REFERENCE CONTROL 2 (MSB) AND IF COUNTER MODE SELECT
MSB D7 0 0 0 D6 0 0 0 D5 0 0 0 1 1 1 0 0 1 1 0 1 0 1 IRC12 IRC11 IRC10 IRC9 IRC8 D4 0 0 0 1 1 1 D3 0 0 0 1 1 1 D2 0 0 0 1 1 1 D1 0 0 1 0 1 1 LSB D0 0 1 0 1 0 1 MSB = 0 MSB = 256 MSB = 512 MSB = 15616 MSB = 15872 MSB = 16128 NOT USED IN APPLICATION MODE IF counter FM mode IF counter AM mode IF counter AM 10.7MHz upconversion mode Bit name Subaddress = 07H FUNCTION
IFCM1 IFCM0 IRC13
fosc/ftim = LSB + MSB + 1
IF COUNTER CONTROL 1
MSB D7 D6 D5 D4 D3 D2 0 0 0 1 1 1 1 X 0 1 FENA FR3 FR2 FR1 FR0 EW2 EW1 EW0 X X X D1 0 0 1 0 0 1 1 LSB D0 0 1 1 0 1 0 1 don't use don't use EW delta f = 6.25kHz (FM); 1kHz (AM; AM-UPC) EW delta f = 12.5kHz (FM); 2kHz (AM; AM-UPC) EW delta f = 25kHz (FM); 4kHz (AM; AM-UPC) EW delta f = 50Hz (FM); 8kHz (AM; AM-UPC) EW delta f = 100kHz (FM); 16kHz (AM; AMUPC) don't use IF counter disabled / stand by IF counter enabled Bit name Subaddress = 08H FUNCTION
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TDA7427
IF COUNTER CONTROL 2
MSB D7 D6 D5 D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 CF3 CF2 CF1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 fcenter = 10.60000MHz (FM) 448KHz (AM) 10.688MHz (AM UPC) fcenter = 10.60625MHz (FM) 449KHz (AM) 10.689MHz (AM UPC) fcenter = 10.61250MHz (FM) 450KHz (AM) 10.690MHz (AM UPC) fcenter = 10.61875MHz (FM) 451KHz (AM) 10.691MHz (AM UPC) fcenter = 10.62500MHz (FM) 452KHz (AM) 10.692MHz (AM UPC) fcenter = 10.63125MHz (FM) 453KHz (AM) 10.693MHz (AM UPC) fcenter = 10.63750MHz (FM) 454KHz (AM) 10.694MHz (AM UPC) fcenter = 10.64375MHz (FM) 455KHz (AM) 10.695MHz (AM UPC) fcenter = 10.65000MHz (FM) 456KHz (AM) 10.696MHz (AM UPC) fcenter = 10.65625MHz (FM) 457KHz (AM) 10.697MHz (AM UPC) fcenter = 10.66250MHz (FM) 458KHz (AM) 10.698MHz (AM UPC) fcenter = 10.66875MHz (FM) 459KHz (AM) 10.699MHz (AM UPC) fcenter = 10.67500MHz (FM) 460KHz (AM) 10.700MHz (AM UPC) fcenter = 10.68125MHz (FM) 461KHz (AM) 10.701MHz (AM UPC) fcenter = 10.68750MHz (FM) 462KHz (AM) 10.702MHz (AM UPC) fcenter = 10.69375MHz (FM) 463KHz (AM) 10.703MHz (AM UPC) fcenter = 10.70000MHz (FM) 464KHz (AM) 10.704MHz (AM UPC) fcenter = 10.70625MHz (FM) 465KHz (AM) 10.705MHz (AM UPC) fcenter = 10.71250MHz (FM) 466KHz (AM) 10.706MHz (AM UPC) fcenter = 10.71875MHz (FM) 467KHz (AM) 10.707MHz (AM UPC) fcenter = 10.72500MHz (FM) 468KHz (AM) 10.708MHz (AM UPC) fcenter = 10.73125MHz (FM) 469KHz (AM) 10.709MHz (AM UPC) fcenter = 10.73750MHz (FM) 470KHz (AM) 10.710MHz (AM UPC) fcenter = 10.74375MHz (FM) 471KHz (AM) 10.711MHz (AM UPC) fcenter = 10.75000MHz (FM) 472KHz (AM) 10.712MHz (AM UPC) fcenter = 10.75625MHz (FM) 473KHz (AM) 10.713MHz (AM UPC) fcenter = 10.76250MHz (FM) 474KHz (AM) 10.714MHz (AM UPC) fcenter = 10.76875MHz (FM) 475KHz (AM) 10.715MHz (AM UPC) fcenter = 10.77500MHz (FM) 476KHz (AM) 10.716MHz (AM UPC) fcenter = 10.78125MHz (FM) 477KHz (AM) 10.717MHz (AM UPC) fcenter = 10.78750MHz (FM) 478KHz (AM) 10.718MHz (AM UPC) fcenter = 10.79375MHz (FM) 479KHz (AM) 10.719MHz (AM UPC) tsample = 160s (FM mode); 1ms (AM; AM-UPC) tsample = 320s (FM mode); 2ms (AM; AM-UPC) tsample = 640s (FM mode); 4ms (AM; AM-UPC) tsample = 1.280ms (FM mode); 8ms (AM; AM-UPC) tsample = 2.560ms (FM mode); 16ms (AM; AM-UPC) tsample = 5.120ms (FM mode); 32ms (AM; AM-UPC) tsample = 10.240ms (FM mode); 64ms (AM; AM-UPC) tsample = 20.480ms (FM mode); 128ms (AM; AM-UPC) CF0 bit same Subaddress = 09H FUNCTION
IFS2 IFS1 IFS0 CF4
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TDA7427
OSCILLATOR ADJUST
MSB D7 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D6 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D5 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X D4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 OSC4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 OSC3 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 OSC2 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 OSC1 LSB D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 OSC0 FUNCTION Cload 1,2 = 3pF Cload 1,2 = 4.25pF Cload 1,2 = 5.5pF Cload 1,2 = 6.75pF Cload 1,2 = 8pF Cload 1,2 = 9.25pF Cload 1,2 = 10.5pF Cload 1,2 = 11.75pF Cload 1,2 = 13pF Cload 1,2 = 14.25pF Cload 1,2 = 15.5pF Cload 1,2 = 16.75pF Cload 1,2 = 18pF Cload 1,2 = 19.25pF Cload 1,2 = 20.5pF Cload 1,2 = 21.75pF Cload 1,2 = 23pF Cload 1,2 = 24.25pF Cload 1,2 = 25.5pF Cload 1,2 = 26.75pF Cload 1,2 = 28pF Cload 1,2 = 29.25pF Cload 1,2 = 30.5pF Cload 1,2 = 31.75pF Cload 1,2 = 33pF Cload 1,2 = 34.25pF Cload 1,2 = 35.5pF Cload 1,2 = 36.75pF Cload 1,2 = 38pF Cload 1,2 = 39.25pF Cload 1,2 = 40.5pF Cload 1,2 = 41.75pF Bit name
Subaddress = 0AH
PORT EXTENSION CONTROL
MSB D7 D6 D2 LSB D0 0 1 FUNCTION CMOS push-pull DOUT1 low CMOS push-pull DOUT1 high NPN opencollector DOUT3 inactive NPN opencollector DOUT3 active always "0" in application mode Bit name Subaddress = 0BH
0 1 0 0 DOUT3 DOUT1
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TDA7427
mm MIN. a1 B b b1 D E e e3 F I L Z 3.3 1.34 8.5 2.54 22.86 7.1 3.93 0.130 0.254 1.39 0.45 0.25 25.4 0.335 0.100 0.900 0.280 0.155 1.65 TYP. MAX. MIN. 0.010 0.055 0.018 0.010 1.000 0.065 inch TYP. MAX.
DIM.
OUTLINE AND MECHANICAL DATA
DIP20
0.053
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TDA7427
mm MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 12.6 7.4 1.27 10.65 0.75 1.27 0.394 0.010 0.016 TYP. MAX. 2.65 0.3 0.51 0.32 13 7.6 MIN. 0.093 0.004 0.013 0.009 0.496 0.291 0.050 0.419 0.030 0.050 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.512 0.299
DIM.
OUTLINE AND MECHANICAL DATA
SO20
0 (min.)8 (max.)
L
h x 45
A B e K H D A1 C
20
11 E
1
1 0
SO20MEC
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TDA7427
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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